In general, a conventional process of fabricating a CMOS semiconductor integrated circuit device that a CMOS circuit is formed on an ordinary silicon substrate requires eight patterns of patterning masks for forming (1) field oxide film, (2) n-well, (3) p-well, (4) gate electrode, (5) p-LDD layer, (6) n-LDD layer, (7) p-source, drain diffusion layers, and (8) n-source, drain diffusion layers, from the start of the process until the formation of transistor before the wiring process.
On the other hand, in a conventional SOI MOSFET fabrication process that a CMOS circuit is formed on a SOI substrate, the number of patterning masks can be reduced to a degree because well-forming steps are not necessary. However, the SOI substrate is more expensive than the silicon substrate. Therefore, for the purpose of reducing the manufacturing cost, it is desired that the number of steps in the SOI MOSFET fabrication process be further decreased.
Also, a CMOS master-slice type semiconductor integrated circuit device comprising an array of basic cells, each of which is composed of several MOSFETs, has been developed.
Thus, the first problem is that the conventional CMOS integrated circuit device using SOI substrate must have a high manufacturing cost. This is because SOI substrates are three to five times expensive comparing to ordinary silicon substrates. Therefore, the cost-down effect in fabricating the conventional CMOS integrated circuit device using SOI substrate, which is brought by that the well-forming process is omitted, is canceled by the high manufacturing cost of SOI substrate.
The second problem is that the integration density of elements must be reduced when the conventional CMOS master-slice type circuit is formed on silicon substrate or SOI substrate. This is because the conductivity type of MOSFET channel cannot be changed in the customizing process. Namely, the conductivity type of active-region channel of MOSFET is determined at the time of well-forming in case of bulk CMOS and at the time of ion-implantation for adjusting Vt in case of SOI CMOS. Thus, the conductivity type of MOSFET channel is determined before the customizing process.